1. Field of the Invention
The present invention relates to the field of semiconductor devices, and more specifically to a gate dielectric layer for semiconductor device and a method of making the same.
2. Description of Related Art
One of the most important features required for the production of future small scaled semiconductor devices is a thin highly reliable insulating layer. The drive for ultra large scale integration (ULSI) implies shrinking of transistor dimensions and consequentially, a need for an ultrathin (&lt;200 .ANG.) highly reliable gate insulator. Additionally, highly reliable dielectrics are required for scaled floating gate memories, because their tunnel oxide film suffers from high field (&gt;8 MV/cm) stress during device operation resulting in the limitation of data retention times as well as read/write cycles.
Scaled semiconductor devices will require thin dielectric layers which exhibit excellent electrical and reliability characteristics. For example, future technologies will require gate dielectric layers with reduced interface state generation and bulk trapping, and improved endurance to charge injection and high breakdown fields. Floating gate memories in particular will require dielectric layers which exhibit reduced trapping and increased "charge to breakdown" in tunneling stress. Additionally, due to high integration and thin layer requirements, future technologies will require a dielectric layer with an extremely uniform and manufacturable process.
Present gate insulating layers fall short of the requirements necessary for future small scale devices. Most conventional gate insulating layers are pure SiO.sub.2 oxide films formed by thermal oxidation. Others employ a combination of a high temperature deposited SiO.sub.2 layer on a thermally grown oxide layer. Pure SiO.sub.2 layers are unsuitable for future devices because their integrity is inadequate when formed to thicknesses below 150 .ANG.. That is, they suffer from their inherent physical and electrical limitations. Still further, SiO.sub.2 layers suffer from their inability to be manufactured uniformly and defect-free when formed thin. Additionally, subsequent ULSI processing steps continue to degrade the already fragile integrity of thin SiO.sub.2 layers. In addition pure SiO.sub.2 layers tend to degrade, when exposed to charge injection, by interface generation and charge trapping. As such, pure SiO.sub.2 layers are simply inadequate as thin films for future scaled technologies.
Nitrided oxides (NO) have recently been proposed as a substitute to pure SiO.sub.2 layers in future semiconductor devices. Nitrided oxides exhibit a number of characteristics such as: improved electrical characteristics under stress, insensitivity to radiation, and a barrier to various dopants, which make them attractive as gate dielectrics for a number of applications. Nitrided oxides are generally formed by first thermally growing an SiO.sub.2 layer and then later exposing the oxide layer to a pure ammonia (NH.sub.3) high temperature anneal in order to nitride the oxide. Unfortunately, nitrided oxides (NO) formed by annealing in pure ammonia (NH.sub.3) suffer from increased electron trapping due to the large amount of ammonia, and hence hydrogen causing traps which are introduced into the dielectric during nitridation.
To combat these problems reoxidation of nitrided oxides (RNO) has been proposed. Reoxidation of nitrided oxides show both a decrease in electron trapping and interface state generation. These improvements are attributed to the incorporation of a relatively small amount of nitrogen at the silicon/dielectric interface without introducing a large amount of hydrogen. The reoxidation process essentially drives in oxygen atoms to drive out excess nitrogen atoms at the insulator/silicon interface which were formed during the nitridation process.
A problem with reoxidized nitrided oxides (RNO) is that because of the way they are formed, they lack a uniform nitrogen concentration at the silicon/insulator interface and the ability to independently control the nitrogen concentration at the silicon/insulator interface and the nitrogen concentration in the bulk of the insulator. Since the nitrogen concentration of the insulator is set by first diffusing a large nitrogen concentration through the oxide layer into the interface (nitridation) and then driving out with oxygen (reoxidation) excess nitrogen, the nitrogen concentration uniformity suffers. Additionally, because the nitrogen concentration in the bulk of the insulator and the nitrogen concentration at the interface are both determined by the same nitridation and subsequent reoxidation process, their nitrogen concentrations can not be independently controlled to optimize electrical characteristics.
Another problem with both NO and RNO films is that they use thermally grown oxides. Thermally grown oxide layers are susceptible to the "Kooi" effect which causes thickness variation in the grown layer. Thickness variations in the oxide layer translates into performance, reliability, and manufacturing problems. Additionaly, many present NO and RNO processes utilize Rapid Thermal Nitridation (RTN) which is a short time, high temperature nitridation process. Such a rapid thermal process can cause wafer warpage, an undesired redistribution of dopants, and the creation of slip dislocations in the crystal lattice.
Thus, what is needed is a thin dielectric layer which can meet the electrical and reliability requirements of future scaled semiconductor devices, and which can be formed easily and uniformly in a ULSI environment.